Most complex integrated circuits (ICs) utilize a clock signal to synchronize different parts of the circuit. Clock distribution is increasingly difficult as ICs become more complex and exhibit ever increasing speed performance. Many ICs generate high-quality clock signals using a class of reference circuits that include phase-locked loops (PLLs) and delay-locked loops (DLLs), collectively “locked-loop circuits.” The following discussion focuses on PLLs, but is equally applicable to DLLs.
A typical PLL generates a stable clock signal using a voltage-controlled oscillator (VCO), the frequency of which is controlled by application of a control voltage. One type of PLL, a charge-pump PLL, adjusts the VCO frequency by moving charge to and from an integration capacitor to vary a control voltage for the VCO. The stored charge and resultant control voltage provide the phase and frequency information that directs the operation of the PLL.
Where a PLL is manufactured using complementary metal-oxide semiconductor (CMOS) processes, the gate capacitance of an n-channel field-effect transistor (FET) can be used as the integration capacitor. As advances are made in CMOS processing technology, however, gate oxide dielectric thickness is becoming thinner. Significant current leakage can occur from the gate electrode, through the thin gate oxide, and to the inversion channel of the transistor. This leakage introduces noise into the control voltage for the VCO, and this noise adversely affects the phase and frequency stability of the VCO.
Current leakage across integration capacitors can be reduced by using capacitors with metal plates. Realizing a capacitor of a given capacitance using a metal plate structure can require many times more semiconductor die area than realizing the capacitor using the gate capacitance of a FET. Moreover, the capacitance of metal plate capacitor structures can vary considerably from die to die and can be difficult to control. Current leakage across integration capacitors can also be reduced by using transistors with thick gate oxides. A transistor with a thick gate oxide, however, provides less capacitance per unit of semiconductor die area as compared to a transistor with a thin gate oxide. There is therefore a need for small, efficient means of controlling the phase and frequency of locked-loop circuits.